The present invention relates to semiconductor device manufacturing technology.
In connection with semiconductor devices of the type incorporated in small size electronic equipment, such as mobile phones, personal digital assistants and mobile personal computers, there is a demand for thin models, compact models and multi-pin models. As an example of semiconductor devices which meet such a demand, CSP (Chip Size Package) type devices are known. Various types of CSP type semiconductor devices have been proposed and commercialized. One of them is a CSP type semiconductor device which is manufactured using wafer packaging technology which combines wafer processing and a package assembly process (hereinafter called a wafer level CSP type semiconductor device). It is easier to make the wafer level CSP type semiconductor device into a compact, low cost model than what is called the chip level CSP type semiconductor device (CSP type semiconductor device which is manufactured by packaging, one by one, semiconductor chips produced by segmenting a semiconductor wafer), because the package flat surface size of the wafer level CSP type semiconductor device is almost equal to the semiconductor chip flat surface size.
The wafer level CSP type semiconductor device mainly includes: a chip layer which corresponds to a semiconductor chip; a rewiring (secondary wiring) layer formed over the main surface of the chip layer; and solder bumps (protruding electrodes) disposed as external connection terminals over the secondary wiring layer. The chip layer includes: a semiconductor substrate; a multilayer wiring layer (primary wiring layer) formed as a laminate of plural insulating layers and plural wiring layers; and a surface protective film which covers the multilayer wiring layer. In the chip layer, electrode pads (bonding pads) are formed over the top wiring layer of the primary wiring layer, and the surface protective film has bonding holes which expose the electrode pads.
The secondary wiring layer is a layer (interposer) designed to arrange electrode pads with larger pitches than electrode pads in the primary wiring layer in order to match the pitches of electrode pads of a wiring board where a semiconductor device is mounted (mounting board). The electrode pads in the secondary wiring layer are electrically connected with the electrode pads in the primary wiring layer. Solder bumps are electrically and mechanically connected with the electrode pads in the secondary wiring layer.
An example of a wafer level CSP type semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 2002-305285 (Patent Literature 1)
In the manufacture of a wafer level CSP type semiconductor device, a semiconductor wafer is segmented to produce individual semiconductor devices (the semiconductor wafer is divided along scribe lines to provide plural semiconductor chips, where each of the chips include an integrated circuit, plural first electrode pads and plural second electrode pads) before a burn-in (aging) step is taken. The burn-in step refers to a screening test (for rejection of devices with inherent defects or potential defect factors) in which the circuit of a semiconductor device is operated under more severe operating conditions (under load) than the customer's usual operating conditions (in a sense, the occurrence of defects is accelerated), with the result that a device which could be treated as defective in the customer's operating condition is rejected at the initial stage, or before shipment to the customer.
In the burn-in step, the semiconductor device is attached to a socket, and the semiconductor device and a burn-in board are electrically connected thorough the socket. Electrical connection between the socket and the semiconductor device is effected by pushing a solder bump of the semiconductor device against the contact pin of the socket. Due to friction at the time of this pressure contact, etc., some solder bump residues adhere to the contact pin. In the burn-in step, plural sockets are repeatedly used, and how many times one socket is used in a day depends on the semiconductor device production volume and the number of sockets in use. One socket may be used several hundreds of times in a day. Each time the socket is used, solder bump residues are accumulated on the contact pin.
Solder bump residues accumulated on the contact pin peel off of the contact pin and, for some reason, adhere to the semiconductor device's mounting surface (surface which faces the substrate during mounting) as foreign matter. Also, solder bump residues which are produced by friction due to contact pressure, etc. adhere to the semiconductor device's mounting surface as foreign matter for some reason.
The wafer level CSP type semiconductor device has a secondary wiring layer (rewiring layer) over the mounting surface, and the secondary wiring layer has plural wires (secondary wires) for electrical connection between the electrode pads in the primary wiring layer and those in the secondary wiring layer. These secondary wires are covered by an insulating layer formed above them. This insulating layer is very thin (for example, 2-3 μm) and the spacing between neighboring wires is small (10 μm or so). Therefore, the following problem may occur: foreign matter adhering to the semiconductor device's mounting surface, as mentioned above, might break and penetrate the insulating layer and touch a secondary wire, resulting in shorting of neighboring secondary wires.
Since adhesion of foreign matter in the burn-in step is unavoidable, removal of foreign matter at the final stage after the burn-in step is indispensable. With the conventional cleaning method, in which foreign matter is manually removed using vacuum tweezers, it has taken a lot of time to remove foreign matter (20 hours/K pieces). This has seriously lowered the working efficiency and contributed to a production cost increase. Besides, in manual removal of foreign matter, the removal performance is unstable, leading to a low product yield.
In the sorting (test) step after the burn-in step in the manufacture of a wafer level semiconductor device, an electrical characteristic evaluation test is conducted to check whether or not the semiconductor device works normally. In this characteristic evaluation test, the semiconductor device and a performance board (testing wiring board) are also electrically connected through a socket. In other words, foreign matter (solder bump residues) may adhere to the mounting surface of the semiconductor device in the sorting step as well.
Segmentation of a semiconductor wafer is usually carried out by dicing. In the manufacture of a chip level CSP type semiconductor device including a wire bonding step, a semiconductor wafer is segmented into plural semiconductor chips by dicing in a clean room. In the manufacture of a wafer level CSP type semiconductor device, a semiconductor wafer is also segmented into plural semiconductor chips by dicing in a clean room. Since steps after segmentation are carried out in a non-clean room, not only solder bump residues, but also other types of foreign matter may adhere to the mounting surface of the semiconductor device.